TS4601
High performance stereo headphone amplifier with capacitorless outputs and I2C bus interface
Features
Power supply range: 2.9 V to 5.5 V 107 dB of PSRR at 217 Hz Fully differential inputs I²C interface for volume control Digital volume control range from -60 dB to +4 dB 101 dB of SNR A-weighted Independent right and left channel shutdown control
TS4601EIJT - Flip-chip
Pinout (top view)
SDZ SDA SCL VOUTR
Low quiescent current: 4.8 mA typ. at 3.0 V Low standby current: 2 A max
INR-
D
Output-coupling capacitors removed Flip-chip package 2.1 mm x 2.1 mm, 500 m pitch, 16 bumps
INL-
INR+
CMS
VCC
C
INL+
PVSS
VOUTL
B
Applications
PVCC
GND
C1 C1
C2
A
Cellular phones Notebook computers CD/MP3 players
4
3
2
1
Balls are underneath
Description
The TS4601 is a stereo headphone driver dedicated to high audio performance and spaceconstrained applications. It is based on low power dissipation amplifier core technology. Special care was taken in the design of the amplification chain to achieve peerless PSRR (107 dB typ. at 217 Hz) and 101 dB of SNR. The TS4601 can drive 0.9 Vrms output voltage into 16 and 1.6 Vrms into 10 k, whatever the power supply voltage, in the 2.9 V to 5.5 V range.
An I²C interface offers volume control in 64 steps from -60 dB to +4 dB and multiple configuration modes for the device. The traditionally used output-coupling capacitors can be removed and a dedicated common-mode sense pin removes parasitic noise from the jack. The TS4601 is designed to be used with an output serial resistor. It ensures unconditional stability over a wide range of capacitive loads. The TS4601 is packaged in a tiny 16-bump flipchip with a pitch of 500 m and a 300 m diameter ball size.
February 2008
Rev 2
1/28
www.st.com 28
Contents
TS4601
Contents
1 2 3 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 3 Typical application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 3.2 Electrical characteristics tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 4.2 Common-mode sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.1 4.2.2 I²C bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Control register CR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 4.4 4.5 4.6 4.7
Wake-up and standby time definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Decoupling considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Low frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Low pass output filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Single-ended input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 6 7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/28
TS4601
Absolute maximum ratings and operating conditions
1
Absolute maximum ratings and operating conditions
Table 1.
Symbol VCC Vin Tstg Tj Rthja Pd ESD Latch-up Supply voltage (1) Input voltage In Master standby mode, and I²C1, 6 and 7 In I²C 2, 3, 4 and 5 Storage temperature Maximum junction temperature Thermal resistance junction to ambient Power dissipation HBM - human body model(4)
(2)
Absolute maximum ratings
Parameter Value 6 0 to VCC -2.4 to +2.4 -65 to +150 150 200 Internally limited(3) kV V mA C Unit V V C C C/W
2 200 200 260
MM - machine model (min. value)(5) Latch-up immunity Lead temperature (soldering, 10sec)
1. All voltage values are measured with respect to the ground pin. 2. The device is protected in case of over temperature by a thermal shutdown active @ 150 C. 3. Exceeding the power derating curves during a long period may provoke abnormal operation. 4. Human body model: A 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5 k resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating. 5. Machine model: A 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 ). This is done for all couples of connected pin combinations while the other pins are floating.
Table 2.
Symbol VCC RL CL Toper Rthja
Operating conditions
Parameter Supply voltage Load resistor Load capacitor Serial resistor of 12 minimum, RL 16, Operating free air temperature range Flip-chip thermal resistance junction to ambient Value 2.9 to 5.5 16 0.8 to 100 -40 to +85 90 Unit V nF C C/W
3/28
Typical application schematics
TS4601
2
Figure 1.
Typical application schematics
Typical application schematics for the TS4601
Vcc Cs 1uF
TS4601
C1
Gnd
Vcc Positive Reg Negative Left Input Gnd Positive Left Input Master Standby Command Positive Right Input Gnd Negative Right Input Cin 2.2uF
C3
Gnd Cout 0.8nF min.
Cin 2.2uF Cin 2.2uF
B4 B3
InLInL+
+
+
VoutL
12 ohms min.
B1
Rout CMS
C2
D4
SDZ InR+ InRSDA SCL I2C Negative Supply Gnd
A3
Gnd 12 ohms min. VoutR
D1
Headphone / Line Out
D3 D2
I2C Bus Vcc
PVcc
A4
C1
A2
C2
A1
Cs 1uF Gnd Gnd
C12 1uF Gnd
Table 3.
Pin description for the TS4601
Pin name VCC PVCC C1 C2 PVSS VOUTR VOUTL GND CMS INLINL+ SDZ INRPin definition Analog supply voltage, connect to Vbattery. Power supply voltage, connect to Vbattery. Capacitor terminal for internal negative supply generator. Capacitor terminal for internal negative supply generator. Capacitor terminal for internal negative supply generator filtering. Right audio channel output signal. Left audio channel output signal. Ground of the device. Common-mode sense, to be connected as close as possible to the ground of headphone / line out plug. Left audio channel negative input signal. Left audio channel positive input signal. Master standby of the circuit. When SDZ = 0, the device is also reset to initial state. Up to VCC tolerant input. Right audio channel negative input signal.
Pin number C1 A4 A2 A1 B2 D1 B1 A3 C2 B4 B3 D4 C4
4/28
Negative Reg PVss
B2
-
Cin 2.2uF
C4
+
+
Rout
Cout 0.8nF min. Gnd
Css 2.2uF
TS4601 Table 3. Pin description for the TS4601 (continued)
Pin name INR+ SDA SCL
Typical application schematics
Pin number C3 D3 D2
Pin definition Right audio channel positive input signal. I²C signal data. Up to VCC tolerant input. I²C clock signal. Up to VCC tolerant input.
Table 4.
Component description for the TS4601
Value Description Decoupling capacitors for VCC and PVCC. Two 1F capacitors are enough for proper decoupling of TS4601. X5R dielectric and 10V rating voltage is recommended to minimize C/V when VCC= 5V. Must be placed as close as possible to the TS4601 to minimize parasitic inductance and resistance. Capacitor for internal negative power supply operation. X5R dielectric and 10V rating voltage is recommended to minimize C/V when VCC= 5V. Must be placed as close as possible to the TS4601 to minimize parasitic inductance and resistance. Filtering capacitor for internal negative power supply. X5R dielectric and 10V rating voltage is recommended to minimize C/V when VCC = 5V. Input coupling capacitor that forms with Zin, a first order high pass filter with a -3dB cut-off frequency FC. Zin is 12k typical and independent of the gain setting. For example FC = 13Hz, Cin = 1F and for FC = 6Hz, Cin = 2.2F Output capacitor of 0.8nF minimum to 100nF maximum. This capacitor is mandatory for operation of the TS4601. Output resistor in series with the TS4601 output. This 12 minimum resistor is mandatory for operation of the TS4601.
Component
Cs
1F
C12
1F
CSS
2.2F
1 C i n = ----------------------2 Z i n F c
Cin
Cout Rout
0.8nF to 100nF 12 min.
5/28
Electrical characteristics
TS4601
3
3.1
Table 5.
Symbol VIL VIH VIL VIH FSCL VOL Iin
Electrical characteristics
Electrical characteristics tables
Electrical characteristics of the I²C interface from VCC=+2.9 V to VCC=+5.5 V, GND = 0 V, Tamb = 25 C (unless otherwise specified)
Parameter Low level input voltage on SDZ pins High level input voltage on SDZ pins Low level input voltage on SDA, SCL pins High level input voltage on SDA, SCL pins I2C clock frequency 1.3 400 0.4 10 480 600 720 1.1 0.6 Min. Typ. Max. 0.63 Unit V V V V kHz V A k
Low level output voltage, SDA pin, Isink = 3mA Input current on SDA, SCL from 0.4V to 4.5V Pull-down resistor on SDZ
Table 6.
Symbol
Electrical characteristics of the amplifier from VCC=+2.9 V to VCC=+5.5 V, GND = 0 V, Tamb = 25 C (unless otherwise specified)
Parameter Quiescent supply current, no input signal, both channels enabled, RL= 16 VCC = 3.0V VCC = 5.0V Master standby current, No input signal VSDZ= 0V VSDZ= 0.35V, VCC= 5V I²C standby current, no input signal Input differential voltage range(1) -5 Min. Typ. Max. Unit
ICC
4.8 5.6 0.5
6 7 2 10 75 1.2 +5
mA
ISTBY ISTBY Vin Voo
A A Vrms mV
Output offset voltage No input signal, RL = 32 Maximum output voltage, in-phase signals RL = 16, THD+N = 1% max, f = 1kHz , RL = 10k, Rs=15 CL=1nF, THD+N = 1% max, f = 1kHz
Vout
0.9 1.6 10 22000
Vrms
Frequency RL = 16, G = 0dB, Pout = 20mW, +/- 0.5dB (related to1kHz) range Cin = 4.7F THD + N Total harmonic distortion + noise, G = 0dB RL = 16, Po = 5mW, F = 1kHz RL = 16, Po = 10mW, 20Hz < F < 20kHz
Hz
0.02 0.2
%
6/28
TS4601 Table 6.
Symbol
Electrical characteristics Electrical characteristics of the amplifier from VCC=+2.9 V to VCC=+5.5 V, GND = 0 V, Tamb = 25 C (unless otherwise specified)
Parameter Power supply rejection F = 217Hz, RL = 16, G = 0dB Vripple = 200mVpp, grounded inputs F = 10kHz, RL = 16, G = 0dB Vripple = 200 mVpp, grounded inputs Common mode rejection ratio RL = 16, F = 20Hz to 20 kHz, G = 0dB, Vic = 200 mVpp Channel separation RL = 16, G = 0dB, F = 1kHz, Po = 40mW RL = 10k, G = 0dB, F = 1kHz, Vout = 1.6Vrms Signal to noise ratio, A-weighted, RL=16 , Vout = 0.9Vrms THD+N < 1%, F = 1kHz, G=+4 dB(3) Output noise voltage, A-weighted G= +4dB G=-19.5dB
(3)
Min.
Typ.
Max.
Unit
ratio(2)
PSRR
100
107 70 65
dB
CMRR
dB
Crosstalk
60 80
82 84 101 -100 -103
dB
SNR
dB dBV dB dB
ONoise G Mute
Gain range with Gain(dB) = 20xlog[(VoutL/R)/(InL/R+ - InL/R-)] InL/R+ - InL/R- = 1Vrms Gain step size from -60dB to -36dB from -36dB to -16.5dB from -16.5dB to +4dB Step size error Gain error (G = +4dB)
-60
+4 -80 3 1.5 0.5
-
dB
-
-1 -0.45 10 20 12 24
+1 +0.42 14.5 29
stepsize dB k
Zin
Left and right channel input impedance all gains setting Single-ended inputs referenced to GND Differential inputs Output impedance in Mode 5 (negative supply is ON and amplifier output stages are OFF)(3) F < 40kHz F = 6MHz F = 36MHz Wake-up time Standby time
Zout
10 500 75 12 10 22
k ms s
twu tSTBY
1. Guaranteed by design and parameter correlation. 2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to VCC @ F = 217 Hz. 3. Guaranteed by design and parameter correlation.
7/28
Electrical characteristics
TS4601
3.2
Electrical characteristic curves
Current consumption vs. power supply voltage Standby current consumption vs. power supply voltage Maximum output power vs. power supply voltage Maximum output power vs. power supply voltage Maximum output voltage vs. power supply voltage PSRR vs. frequency PSRR vs. gain setting THD+N vs. output power THD+N vs. output voltage THD+N vs. frequency THD+N vs. frequency CMRR vs. frequency Crosstalk vs. frequency Common mode response vs. frequency THD+N vs. input voltage. Line in mode 5 Input impedance vs. frequency. Line in mode 5 Gain vs. frequency see Figure 2 see Figure 3 and Figure 4 see Figure 5 see Figure 6 see Figure 7 see Figure 8 to Figure 12 see Figure 13 see Figure 14 to Figure 25 see Figure 26 see Figure 27 see Figure 28 to Figure 39 see Figure 40 and Figure 41 see Figure 42 to Figure 45 see Figure 46 see Figure 47 see Figure 48 see Figure 49
Note:
When the label "RC network" is present in a curve, it means that a 12 + 1 nF low pass filter connected on outputs is used (refer to Figure 1: Typical application schematics for the TS4601 on page 4).
8/28
TS4601
Electrical characteristics
Figure 2.
Current consumption vs. power supply voltage
Mode 4 Mode 2, 3
Figure 3.
Standby current consumption vs. power supply voltage
100 90
6.0 5.5
Current Consumption (mA)
1000
Current Consumption SDZ=Gnd (nA)
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 No load 1.0 SDZ = Vcc SDA = SCL = Vcc 0.5 Ta = 25C 0.0 3.0 3 .5 Mode 5
800
Mode 1, 6, 7, 8
80 70
600
60 50
400 SDZ=Gnd
40 30
4.0
4 .5
5.0
5 .5
200 No load SDA = SCL = Vcc Ta = 25C 0 3.0 3 .5
20 10 0
4.0
4 .5
5.0
5 .5
Power Supply Voltage (V)
Power Supply Voltage (V)
Figure 4.
Standby current consumption vs. standby voltage
Figure 5.
Maximum output power vs. power supply voltage
1E-3
300 275 250 225
Output power (mW)
Current Consumption (nA)
Vcc=5V 1E-4
RL = 16, F = 1kHz Left & Right BW < 30kHz, Tamb = 25C
THD+N=10% (180)
200 175 150 125 100 75 50 25 0 3.0 3 .5 4.0 4 .5 Vcc (V) 5.0 5 .5 THD+N=10% (0) THD+N=1% (180) THD+N=1% (0)
Vcc=2.9V 1E-5
Vcc=3.6V
1E-6 No load SDA = SCL = Vcc Ta = 25C 1E-7 0.0 0 .5 1.0 1 .5 2.0 2 .5 3.0 3 .5 SDZ Voltage (V) 4.0 4 .5 5.0
Figure 6.
Maximum output power vs. power supply voltage
Figure 7.
Maximum output voltage vs. power supply voltage
175 150
Output power (mW)
3.0 RL = 32, F = 1kHz Left & Right BW < 30kHz, Tamb = 25C
Output Voltage (Vrms)
2.5 2.0 1.5 1.0 0.5
RL = RC network + 10k, F = 1kHz Left & Right BW < 30kHz, Tamb = 25C
125 100 75 50 25 0 THD+N=1% (0) 3.0 3 .5 4.0 4 .5 Vcc (V) 5.0 5 .5 THD+N=10% (180) THD+N=10% (0) THD+N=1% (180)
THD+N=10% (0 & 180) THD+N=1% (0 & 180)
0.0
3.0
3 .5
4.0
4 .5 Vcc (V)
5.0
5 .5
9/28
Current Consumption SDZ=Vcc ( A)
Electrical characteristics
TS4601
Figure 8.
0 -10 -20 -30
PSRR (dB)
PSRR vs. frequency
Figure 9.
PSRR vs. frequency
-50 -60 -70 -80 -90 -100 -110 -120 20
Vcc=2.9V
Vcc=3.6V Vcc=5V 100 1000 Frequency (Hz) 10000 20k
Figure 10. PSRR vs. frequency
0 -10 -20 -30
PSRR (dB)
Figure 11. PSRR vs. frequency
0 -10 Vripple = 200mVpp -20 G = 4dB -30 Inputs = grounded -40 Left & Right -50 RL = RC network + 32 Tamb = 25C -60 Vcc=2.9V -70 -80 -90 -100 Vcc=3.6V -110 Vcc=5V -120 -130 20 100 1000 10000 20k Frequency (Hz)
-50 -60 -70 -80 -90 -100 -110 -120 20
Vcc=2.9V
Vcc=3.6V Vcc=5V 100 1000 Frequency (Hz) 10000 20k
Figure 12. PSRR vs. frequency
0 -10 -20 -30
PSRR (dB)
Figure 13. PSRR vs. gain setting
0 Vripple = 200mVpp F = 217Hz RL 16 Vcc = 2.9V to 5.5V Ta = 25C
-50 -60 -70 -80 -90 -100 -110 -120 20
Vcc=2.9V
PSRR (dB)
-40
Vripple = 200mVpp G = 4dB Inputs = grounded Left & Right RL = RC network + 10k Tamb = 25C
PSRR (dB)
-40
Vripple = 200mVpp G = 4dB Inputs = grounded Left & Right RL = 32 Tamb = 25C
PSRR (dB)
-40
Vripple = 200mVpp G = 4dB Inputs = grounded Left & Right RL = 16 Tamb = 25C
0 -10 Vripple = 200mVpp -20 G = 4dB -30 Inputs = grounded -40 Left & Right -50 RL = RC network + 16 Tamb = 25C -60 Vcc=2.9V -70 -80 -90 -100 Vcc=3.6V -110 -120 Vcc=5V -130 20 100 1000 10000 20k Frequency (Hz)
-20 -40 -60 -80
Left & Right
Vcc=3.6V Vcc=5V 100 1000 Frequency (Hz) 10000 20k
-100 -120 -80
-6 0
-40 -2 0 Gain setting (dB)
04
10/28
TS4601
Electrical characteristics
Figure 14. THD+N vs. output power
10 RL = 16 Vcc = 5V G = 4dB 1 Inputs = 0 Left & Right BW < 30kHz Tamb = 25C 0.1
F=80Hz
Figure 15. THD+N vs. output power
10 RL = 16 Vcc = 5V G = 4dB 1 Inputs = 180 Left & Right BW < 30kHz Tamb = 25C 0.1
F=80Hz F=1kHz
THD+N (%)
F=8kHz
THD+N (%)
F=8kHz
0.01 1
F=1kHz
0.01 1 10 100 Output Power (mW)
10 100 Output Power (mW)
Figure 16. THD+N vs. output power
10 RL = 16 Vcc = 3.6V G = 4dB 1 Inputs = 0 Left & Right BW < 30kHz Tamb = 25C 0.1
F=80Hz
Figure 17. THD+N vs. output power
10 RL = 16 Vcc = 3.6V G = 4dB 1 Inputs = 180 Left & Right BW < 30kHz Tamb = 25C
F=1kHz
THD+N (%)
THD+N (%)
F=8kHz
F=8kHz
0.1
0.01 1
F=1kHz
0.01
F=80Hz
10 100 Output Power (mW)
1
10 100 Output Power (mW)
Figure 18. THD+N vs. output power
10 RL = 16 Vcc = 2.9V G = 4dB 1 Inputs = 0 Left & Right BW < 30kHz Tamb = 25C 0.1
Figure 19. THD+N vs. output power
10 RL = 16 Vcc = 2.9V G = 4dB 1 Inputs = 180 Left & Right BW < 30kHz Tamb = 25C 0.1
THD+N (%)
THD+N (%)
F=8kHz
F=8kHz F=1kHz
F=80Hz
0.01 1
F=1kHz
0.01 100 1 10 Output Power (mW)
F=80Hz
10 Output Power (mW)
100
11/28
Electrical characteristics
TS4601
Figure 20. THD+N vs. output power
10 RL = 32 Vcc = 5V G = 4dB 1 Inputs = 0 Left & Right BW < 30kHz Tamb = 25C 0.1
F=1kHz
Figure 21. THD+N vs. output power
10 RL = 32 Vcc = 5V G = 4dB 1 Inputs = 180 Left & Right BW < 30kHz Tamb = 25C 0.1
F=1kHz
THD+N (%)
F=8kHz
THD+N (%)
F=8kHz
0.01 1
F=80Hz
0.01 100 1
F=80Hz
10 Output Power (mW)
10 Output Power (mW)
100
Figure 22. THD+N vs. output power
10 RL = 32 Vcc = 3.6V G = 4dB 1 Inputs = 0 Left & Right BW < 30kHz Tamb = 25C 0.1
F=1kHz
Figure 23. THD+N vs. output power
10 RL = 32 Vcc = 3.6V G = 4dB 1 Inputs = 180 Left & Right BW < 30kHz Tamb = 25C 0.1
F=1kHz
THD+N (%)
F=8kHz
THD+N (%)
F=8kHz
0.01 1
F=80Hz
0.01 100 1 10 Output Power (mW)
F=80Hz
10 Output Power (mW)
100
Figure 24. THD+N vs. output power
10 RL = 32 Vcc = 2.9V G = 4dB 1 Inputs = 0 Left & Right BW < 30kHz Tamb = 25C 0.1
F=1kHz
Figure 25. THD+N vs. output power
10 RL = 32 Vcc = 2.9V G = 4dB 1 Inputs = 180 Left & Right BW < 30kHz Tamb = 25C 0.1
F=1kHz
THD+N (%)
F=8kHz
THD+N (%)
F=8kHz
0.01
F=80Hz
0.01
F=80Hz
1
10 Output Power (mW)
100
1
10 Output Power (mW)
100
12/28
TS4601
Electrical characteristics
Figure 26. THD+N vs. output voltage
10 RL = RC network + 10k Vcc = 2.9V to 5.5V, G = 4dB Inputs = 0 & 180 Left & Right BW < 30kHz, Tamb = 25C
Figure 27. THD+N vs. frequency
1
RL = RC network + 10k Vcc = 2.9V to 5.5V G = 4dB Inputs = 0 & 180 Left & Right Bw < 30kHz 0.1 Tamb = 25C
1
THD+N (%)
THD + N (%)
F=1kHz
Vo=1.5Vrms
0.1
F=8kHz
0.01
F=80Hz
0.01
Vo=30mVrms
Vo=400mVrms
1E-3 10
100 1000 Output Voltage (mVrms)
20
100
1000 Frequency (Hz)
10000 20k
Figure 28. THD+N vs. frequency
1 RL = 16 Vcc = 5V, G = 4dB Inputs = 0 Left & Right Bw < 30kHz 0.1 Tamb = 25C
Figure 29. THD+N vs. frequency
1 RL = 16 Vcc = 5V, G = 4dB Inputs = 180 Left & Right Bw < 30kHz 0.1 Tamb = 25C
THD + N (%)
Po=70mW
THD + N (%)
Po=70mW
0.01 100 1000 Frequency (Hz)
Po=10mW
0.01 100 1000 Frequency (Hz)
Po=10mW
20
10000 20k
20
10000 20k
Figure 30. THD+N vs. frequency
1 RL = 16 Vcc = 3.6V, G = 4dB Inputs = 0 Left & Right Bw < 30kHz 0.1 Tamb = 25C
Figure 31. THD+N vs. frequency
1 RL = 16 Vcc = 3.6V, G = 4dB Inputs = 180 Left & Right Bw < 30kHz 0.1 Tamb = 25C
THD + N (%)
THD + N (%)
Po=70mW
Po=70mW
0.01 100 1000 Frequency (Hz)
Po=10mW
0.01 100 1000 Frequency (Hz)
Po=10mW
20
10000 20k
20
10000 20k
13/28
Electrical characteristics
TS4601
Figure 32. THD+N vs. frequency
1 RL = 16 Vcc = 2.9V G = 4dB Inputs = 0 Left & Right 0.1 Bw < 30kHz Tamb = 25C
Figure 33. THD+N vs. frequency
1 RL = 16 Vcc = 2.9V G = 4dB Inputs = 180 Left & Right 0.1 Bw < 30kHz Tamb = 25C
Po=50mW
THD + N (%)
THD + N (%)
Po=50mW
Po=10mW
0.01 100 1000 Frequency (Hz) 10000 20k
0.01 100 1000 Frequency (Hz)
Po=10mW
20
20
10000 20k
Figure 34. THD+N vs. frequency
1 RL = 32 Vcc = 5V G = 4dB Inputs = 0 Left & Right 0.1 Bw < 30kHz Tamb = 25C
Figure 35. THD+N vs. frequency
1 RL = 32 Vcc = 5V G = 4dB Inputs = 180 Left & Right 0.1 Bw < 30kHz Tamb = 25C
THD + N (%)
Po=60mW
THD + N (%)
Po=60mW
0.01 100 1000 Frequency (Hz)
Po=10mW
0.01 100 1000 Frequency (Hz)
Po=10mW
20
10000 20k
20
10000 20k
Figure 36. THD+N vs. frequency
1 RL = 32 Vcc = 3.6V G = 4dB Inputs = 0 Left & Right 0.1 Bw < 30kHz Tamb = 25C
Figure 37. THD+N vs. frequency
1 RL = 32 Vcc = 3.6V G = 4dB Inputs = 180 Left & Right 0.1 Bw < 30kHz Tamb = 25C
THD + N (%)
Po=60mW
THD + N (%)
Po=60mW
0.01 100 1000 Frequency (Hz)
Po=10mW
0.01 100 1000 Frequency (Hz)
Po=10mW
20
10000 20k
20
10000 20k
14/28
TS4601
Electrical characteristics
Figure 38. THD+N vs. frequency
1 RL = 32 Vcc = 2.9V G = 4dB Inputs = 0 Left & Right 0.1 Bw < 30kHz Tamb = 25C
Figure 39. THD+N vs. frequency
1 RL = 32 Vcc = 2.9V G = 4dB Inputs = 0 Left & Right 0.1 Bw < 30kHz Tamb = 25C
THD + N (%)
Po=50mW
THD + N (%)
Po=50mW
0.01 100 1000 Frequency (Hz)
Po=10mW
0.01 100 1000 Frequency (Hz)
Po=10mW
20
10000 20k
20
10000 20k
Figure 40. CMRR vs. frequency
0 -10 -20
CMRR (dB)
Vic = 200mVpp G = 4dB Left & Right RL 16 Tamb = 25C
Figure 41. CMRR vs. frequency
0 -10 -20
CMRR (dB)
Vic = 200mVpp G = 0dB Left & Right RL 16 Tamb = 25C
-30 -40 -50 -60 -70 -80 20
-30 -40 -50 -60 -70
Vcc=2.9V to 5.5V
Vcc=2.9V to 5.5V
100
1000 Frequency (Hz)
10000 20k
-80 20
100
1000 Frequency (Hz)
10000 20k
Figure 42. Crosstalk vs. frequency
100 90 80
Crosstalk (dB)
Figure 43. Crosstalk vs. frequency
100
Right to Left
90 80
Crosstalk (dB)
Right to Left
70 60 50 40 30 20 10
Left to Right
70 60 50 40 30 20 10
Left to Right
G = 4dB Vcc = 5V Pout = 40mW RL = 16 Tamb = 25C 100 1000 Frequency (Hz) 10000 20k
G = 4dB Vcc = 3.6V Pout = 40mW RL = 16 Tamb = 25C 100 1000 Frequency (Hz) 10000 20k
0 20
0 20
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Electrical characteristics
TS4601
Figure 44. Crosstalk vs. frequency
100 90 80
Crosstalk (dB)
Figure 45. Crosstalk vs. frequency
100
Right to Left
90 80
Crosstalk (dB)
Right to Left
70 60 50 40 30 20 10
Left to Right
70 60 50 40 30 20 10
Left to Right
G = 4dB Vcc = 2.9V Pout = 40mW RL = 16 Tamb = 25C 100 1000 Frequency (Hz) 10000 20k
G = 4dB Vcc = 2.9V to 5.5V Vout = 1.6Vrms RL = RC network + 10k Tamb = 25C 100 1000 Frequency (Hz) 10000 20k
0 20
0 20
Figure 46. Common mode response vs. frequency
0 -10
CMS response : Vout/VCMS (dB)
Figure 47. THD+N vs. input voltage. Line in mode 5
10 Mode 5 Vcc = 2.9V to 5.5V Zout generator = 1k BW < 30kHz, Tamb = 25C
Line In F=80Hz, 1kHz, 8kHz
-20 -30 -40 -50 -60
THD+N (%)
VCMS = 20mVrms G = All gains Left & Right RL 16 Tamb = 25C
1
0.1
0.01
Vcc=2.9V to 5.5V -70
1E-3
Reference F=80Hz, 1kHz, 8kHz
-80 20
100
1000 Frequency (Hz)
10000 20k
1E-4 1E-3
0.01 0.1 Input Voltage (Vrms)
1
Figure 48. Input impedance vs. frequency. Line in mode 5
Mode 5 Vcc = 2.9V to 5.5V Vin = 1Vrms Tamb = 25C
Figure 49. Gain vs. frequency
4 2 0
G a in ( d B )
Zin from outputs (k )
10
RL=16, Po=20mW
-2 -4 -6 -8 -10 10
RL=RC network+10k, Vo=1Vrms Vcc = 2.9V to 5.5V G = 0dB Cin = 4.7F Left & Right Tamb = 25C 100 1000 10000 Frequency (Hz) 10 0 0
1
0.1 0.1 1 10 100 1000 Frequency (kHz) 10000
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TS4601
Application information
4
4.1
Application information
Common-mode sense
The TS4601 implements a common-mode sense to correct the voltage differences that might occur between the headphone jack return and the GND of the device, thus creating parasitic noise in the headphone and/or line-out. The solution to strongly reduce and practically eliminate this noise, is to connect the headphone jack ground to the CMS of the device that is a common-mode sense pin. It will sense the difference of potential (voltage noise) between the TS4601 ground and headphone ground. Thanks to CMS frequency response (refer to Figure 46 on page 16), this noise is removed from the TS4601 outputs. Figure 1: Typical application schematics for the TS4601 illustrates this connection.
4.2
I²C bus interface
In compliance with the I²C protocol, the TS4601 uses a serial bus to control the chip's functions with two wires: Clock (SCL) and Data (SDA). The clock line and the data line are bi-directional (open-collector) with an external chip pull-up resistor (typically 10 k). The maximum clock frequency in fast-mode specified by the I²C standard is 400 kHz, which TS4601 supports. In this application, the TS4601 is always the slave device and the controlling microcontroller MCU is the master device. The slave address of the TS4601 is 1100 000x (C0h). An SDZ pin is available to shut down the circuit from a master MCU. Table 7 summarizes the pin descriptions for the I²C bus interface. Table 7.
Pin SDA SCL SDZ Serial data pin Clock input pin Master standby of the TS4601
I²C bus interface pin descriptions
Functional description
4.2.1
I²C bus operation
The host MCU can write into the TS4601 control register to control the TS4601, and read from the control register to get a configuration from the TS4601. The TS4601 is addressed by the byte consisting of the 7-bit slave address and R/W bit. Table 8.
A6 1
The first byte after the START message for addressing the device
A5 1 A4 0 A3 0 A2 0 A1 0 A0 0 R/W X
There are five control registers (see Table 9) named CR0 to CR4. In read mode, all the control registers can be accessed. In write mode, only CR1 and CR2 can be addressed.
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Application information Table 9. Control registers summary
D7 SC_L D6 SC_R Output modes Mute_L 0 0 Mute_R 0 1 0 0 0 0 D5 T_SH D4 0 0 D3 0 0 D2 0 0 D1 0 0
TS4601
Description
CR0 CR1 - modes CR2 - volume control CR3 CR4 - identification
D0 0 0
Volume control 0 0 0 0 0 0 0 1
To write in the control registers:
In order to write data into the TS4601, after the "start" message, the MCU must:
send byte with the I²C 7-bit slave address and with a low level for the R/W bit send the data (control register setting)
All bytes are sent with MSB first. The transfer of written data ends with a "stop" message. When transmitting several data, the data can be written with no need to repeat the "start" message and addressing byte with the slave address. When writing several bytes, the data is transmitted as follows:
CR1 CR2 CR2 CR2... this is an advantage for a fast increase/decrease of the volume control.
Figure 50. I²C write operations
SLAVE ADDRESS SDA S 1 1 0 0 0 0 0 0 A D7 D6 D1 D0 A D7 D6 D1 D0 A D7 D6 D1 D0 A P CONTROL REGISTERS CR1 CR2 CR2
Start condition R/W Acknowledge from Slave
Stop condition Acknowledge from Slave
To read from the control registers:
In order to read data from the TS4601, after the "start" message, the MCU must:
send byte with the I²C 7-bit slave address and with a high level for the R/W bit receive the data (control register value)
All bytes are read with MSB first. The transfer of read data ends with the "stop" message. When transmitting several data, the data can be read with no need to repeat the "start" message and the byte with the slave address. In this case, the value of the control register is read repeatedly, CR0, CR1, CR2, CR3, CR4, CR0, CR1 etc.
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TS4601 Figure 51. I²C read operations
CONTROL REGISTERS SLAVE ADDRESS SDA S 1 1 0 0 0 0 0 1 A D7 CR0 CR1 D0 A D7 D0 A D7 CR2 D0 A D7 CR3
Application information
CR4 D0 A D7 D0 A P
Start condition R/W Acknowledge from Slave Acknowledge
Stop condition
4.2.2
Table 10.
Control registers
Output mode configuration - CR1
Headphone output Headphone output Left Right Mode 1: standby Mode 2: channel R Mode 3: channel L Mode 4: on Mode 5: Line-in mode Mode 6: standby Mode 7: standby Mode 8: standby SD(1) SD GxINL GxINL SD SD SD SD SD GxINR SD GxINR SD SD SD SD Negative supply and regulators SD ON ON ON ON SD SD SD
Modes register 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
1. SD: shutdown,I NR: audio input right, INL: audio input left, G: gain for channel R and channel L, ON: when a function is active.
The TS4601 can be set to standby in two different ways:
A master standby from an MCU using SDZ input, can set the TS4601 in master standby. The lowest current consumption (Istby=2 A maximum) is achieved with a 0 V on SDZ. At 0.63 V, Istby is 20 A maximum. Note that the SDZ input has a 600 k +/-20% pull-down resistor. If VSDZ > 0 V, an additional current consumption has to be taken into consideration and provided by the MCU IO. This additional current is VSDZ/600k (+/-20%). During master standby mode, amplifiers, power management and I2C part are disabled thus offering the most current-saving standby mode. The TS4601 can also be set to I²C standby by an I²C command. In this case the Istby is slightly higher and is Istby=75 A maximum (including current consumption on SDA and SCL inputs).
When the TS4601 is in Master standby or I²C standby mode (on one or both channels), the corresponding amplifier output is forced to ground through a 16 resistor. In mode 5, in which amplifiers are inactive but the power management part is active, the amplifier outputs are in high impedance state to allow line in function.
19/28
Application information Table 11. Volume control register - CR2
Volume control range: -60 dB to +4 dB D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gain (in dB) Mute: -80dB -60dB -57dB -54dB -51dB -48dB -45dB -42dB -39dB -36dB -34.5dB -33dB -31.5dB -30dB -28.5dB -27dB -25.5dB -24dB -22.5dB -21dB -19.5dB -18dB -16.5dB -16dB -15.5dB -15dB -14.5dB -14dB -13.5dB -13dB -12.5dB -12dB D5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
TS4601
Gain (in dB) -11.5dB -11dB -10.5dB -10dB -9.5dB -9dB -8.5dB -8dB -7.5dB -7dB -6.5dB -6dB -5.5dB -5dB -4.5dB -4dB -3.5dB -3dB -2.5dB -2dB -1.5dB -1dB -0.5dB 0dB 0.5dB 1dB 1.5dB 2dB 2.5dB 3dB 3.5dB 4dB
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TS4601
Application information In the volume register, MUTE_L, and MUTE_R are dedicated bits to enable the mute independently from the channel. When MUTE_L, MUTE_R are set to VIH, the mute function is enabled on the corresponding channel. When MUTE_L, MUTE_R are set to VIL, the gain level is applied to the channel.
Control register CR0
Amplifier output short-circuit detection: The outputs of the amplifier are protected against short-circuits that might occur accidentally during manipulation of the device. In the typical application, if a short-circuit arises on the jack plug, there is no detection due to the serial resistor present on the amplifier output, thus the output current threshold is not reached. To be active, the detection has to occur directly on the amplifier output with a signal modulation on the inputs of the TS4601. If a short-circuit is detected on one channel, a flag is raised in the I²C read register CR0.
SC_L: equals 0 during normal operation, equals 1 when a short-circuit is detected on the left channel SC_R: equals 0 during normal operation, equals 1 when a short-circuit is detected on the right channel
The corresponding channel output stage is then set to high impedance mode. An I²C read command allows the reading of the SC_L and SC_R flags but does not reset them. An I²C write command has to be sent to reset the flags to 0 and restore normal operation. When the TS4601 is in I²C standby mode, the SC_L and SC_R flags are in an undetermined state. Thermal shutdown protection: A thermal shutdown protection is implemented to protect the device from overheating. If the temperature rises above the thermal junction of 150C, the device is put into standby mode and a flag is raised in the read register CR0.
T_SH: equals 0 during normal operation, equals 1 when a thermal shutdown is detected.
When the temperature decreases to safe levels, the circuit switches back to normal operation and the corresponding flag is cleared.
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Application information
TS4601
4.3
Wake-up and standby time definition
The wake-up time of the TS4601 is guaranteed at 12 ms typical (refer to Section 3.1: Electrical characteristics tables on page 6). However, as the TS4601 is activated with an I2C bus, the wake-up start procedure is as follows: 1. 2. 3. 4. 5. 6. The master sends a start bit The master sends the address. The slave (TS4601) answers by an acknowledge. The master sends the output mode configuration (CR1). If the TS4601 was in I2C standby (mode 1, 6, 7), the wake-up starts on the falling edge of the eighth clock signal (SCL) corresponding to CR1 byte. 12 ms after (de-pop sequence time), the TS4601 outputs are operational.
The standby time is guaranteed as 10 s typical (refer to Section 3.1: Electrical characteristics tables on page 6). However, as the TS4601 is de-activated with an I2C bus, the standby time operates as follows: 1. 2. 3. 4. 5. 6. The master sends a start bit The master sends the address. The slave (TS4601) answers by an acknowledge. The master sends the output mode configuration (CR1) and in this case it corresponds to mode 1, 6, 7. The standby time starts on the falling edge of the eighth clock signal (SCL) corresponding to CR1 byte. After 10 s, the TS4601 is in standby mode.
4.4
Decoupling considerations
The TS4601 needs two decoupling capacitors for the positive power supply (battery) and two capacitors for normal operation of the internal negative supply (refer to Figure 1: Typical application schematics for the TS4601 on page 4). These capacitors must be placed as close as possible of the TS4601 to minimize parasitic inductance and resistance that have a negative impact on audio performance. Two decoupling capacitors (Cs) of 1 F and low ESR are recommended for positive power supply decoupling. Packages like the 0402 or 0603 are also recommended because the placement close to TS4601 is easier. X5R dielectric for capacitor tolerance behavior and 10 V DC rating voltage for 5 V operation or 6.3 V DC rating operation for 3.6 V operation to take into consideration the C/V variation of this type of dielectric. Two decoupling capacitors (C12 and Css) of respectively 1 F and 2.2 F and low ESR are recommended for internal negative power supply decoupling. Packages like the 0402 or 0603 are also recommended because the placement close to TS4601 is easier. X5R dielectric for capacitor tolerance behavior and 10 V DC rating voltage for 5 V operation or 6.3 V DC rating operation for 3.6 V operation to take into consideration the C/V variation of this type of dielectric.
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TS4601
Application information
4.5
Low frequency response
Input coupling capacitors Cin (see Figure 1: Typical application schematics for the TS4601 on page 4) are mandatory for TS4601 operation. Cin with Zin (see Section 3.1: Electrical characteristics tables on page 6) form a first order high pass filter and the -3 dB cut-off frequency is:
1 F c ( 3 d B ) = ----------------------2 Z i n C i n
Zin is the single-ended input impedance. Because Zin is independent from the gain setting, determining the appropriate Cin is very simple. However, the tolerance of Zin (refer to Section 3.1: Electrical characteristics tables on page 6) must be taken into consideration for determining Cin. Therefore, for a given Fc, the value of Cin is given by the following equation:
C · = 1-- C ---6 = 1------- C i n = 1-- ---3.3 ---1 i nm i n F i nt y p max Fc F c c
(With Cin in F and Fc in Hz).
4.6
Low pass output filter
The TS4601 is designed to operate with a passive first order low pass filter (see Figure 1: Typical application schematics for the TS4601 on page 4). This low pass filter is mandatory to ensure stability of the TS4601. Rout must have a value of 12 minimum and Cout a value of 0.8 nF minimum up to 100 nF maximum. Values of 12 and 1 nF are a good start point for a design able to drive a classic headphone (16 32 60 ) and the line-in of any Hi-fi system or sound card. The cut-off , , frequency of this filter (12 and 1 nF) is about 13 MHz and clearly above the audio band.
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Application information
TS4601
4.7
Single-ended input configuration
The TS4601 can be used in single-ended input configuration. InR- and InL- must be shorted to ground through input capacitors. All Cin capacitors must have the same value to keep the same PSRR performance as in differential input configuration. Figure 52 shows an example.
Figure 52. Typical application schematics for the TS4601 in single-ended input
Vcc Cs 1uF
TS4601
C1
Gnd
Vcc Positive Reg Gnd Cin 2.2uF Cin 2.2uF Gnd Cout 0.8nF min.
B4 B3
InLInL+
+
+
VoutL
12 ohms min.
B1
Left Input Master Standby Command Right Input
Rout CMS
C2
D4
SDZ InR+ InRSDA SCL I2C Negative Supply Gnd
A3
Cin 2.2uF
C3
Gnd 12 ohms min. VoutR
D1
Headphone / Line Out
Gnd
D3 D2
I2C Bus Vcc
PVcc
A4
C1
A2
C2
A1
Cs 1uF Gnd Gnd
C12 1uF Gnd
The gain in this configuration is given by:
Vo u t L G a i n ( d B ) = 20 log ------------------------ V i n p u t L e f t
or :
Vo u t R G a i n ( d B ) = 20 log --------------------------- V i n p u t R i g h t
24/28
Negative Reg PVss
B2
-
Cin 2.2uF
C4
+
+
Rout
Cout 0.8nF min. Gnd
Css 2.2uF
TS4601
Package information
5
Package information
In order to meet environmental requirements, STMicroelectronics offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics trademark. ECOPACK specifications are available at: www.st.com. Figure 53. TS4601 footprint recommendation
500m =250m 500m 75m min. 100m max. Track
500m
=400m typ. =340m min.
150m min.
Non Solder mask opening
500m
Pad in Cu 18m with Flash NiAu (2-6m, 0.2m max.)
Figure 54. Pinout Top view
SDZ SD A SCL VOUTR
Bottom view
D D
VOUTR SCL SDA SDZ
INR-
INR+
CMS
VCC
C
C
VCC
CMS
INR+
INR-
INL-
INL+
PVSS
VOUTL
B
B
VOUTL
PVSS
INL+
INL-
PVCC
GND
C1
C2
A
A
C2
C1
GND
PVCC
4
3
2
1
1
2
3
4
Balls are underneath
25/28
Package information Figure 55. Marking (top view)
TS4601
Logo: ST Symbol for lead-free: E Part number: 01 X digit: Assembly code Date code: YWW The dot marks pin A1
01X YWW E
Figure 56. Flip-chip - 16 bumps
2100m
2100 m
Die size: 2.1mm x 2.1mm 30m Die height (including bumps): 600m Bumps diameter: 315m 50m Bump diameter before reflew: 300m 10m Bump height: 250m 40m Die height: 350m 20m Pitch: 500m 50m Coplanarity: 60m max
500m
500m
600m
Figure 57. Device orientation in the tape pocket
1 A A
Die size Y + 70m
1
8
Die size X + 70m
4
All dimensions are in mm
User direction of feed
26/28
TS4601
Ordering information
6
Ordering information
Table 12. Order codes
Temperature range -40 C to +85 C Package Flip-chip Packing Tape & reel Marking 01
Order code TS4601EIJT
7
Revision history
Table 13.
Date 15-Jan-2008 20-Feb-2008
Document revision history
Revision 1 2 Changes Initial release, preliminary information. Complete datasheet for release to market of the device.
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TS4601
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