L4974A
3.5A SWITCHING REGULATOR
. . . . . . . . . . . . . .
3.5A OUTPUT CURRENT 5.1V TO 40V OUTPUT VOLTAGE RANGE 0 TO 90% DUTY CYCLE RANGE INTERNAL FEED-FORWARD LINE REG. INTERNAL CURRENT LIMITING PRECISE 5.1V 2% ON CHIP REFERENCE RESET AND POWER FAIL FUNCTIONS INPUT/OUTPUT SYNC PIN UNDER VOLTAGE LOCK OUT WITH HYSTERETIC TURN-ON PWM LATCH FOR SINGLE PULSE PER PERIOD VERY HIGH EFFICIENCY SWITCHING FREQUENCY UP TO 200KHz THERMAL SHUTDOWN CONTINUOUS MODE OPERATION
MU L T I PO W ER BCD TECHNOLOGY
P OW E R D I P (16 + 2 + 2) ORDERING NUMBER : L4974A
D E SC R I P T I O N The L4974A is a stepdown monolithic power switching regulator delivering 3.5A at a voltage variable from 5.1 to 40V. Realized with BCD mixed technology, the device uses a DMOS output transistor to obtain very high efficiency and very fast switching times. Features of B L O C K DIAGRAM
the L4974A include reset and power fail for microprocessors, feed forward line regulation, soft start, limiting current and thermal protection. The device is mounted in a Powerdip 16 + 2 + 2 plastic package and requires few external components. Efficient operation at switching frequencies up to 200KHz allows reduction in the size and cost of external filter component.
June 2000
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This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L497 4A
A B SO L U T E MAXIMUM RATINGS
S ym b o l V11 V11 V20 I20 VI V4, V8 V3 I3 V2, V7, V9, V10 I2 I7 I8 Ptot TJ, Tstg Input Voltage Input Operating Voltage Output DC Voltage Output Peak Voltage at t = 0.1s f = 200khz Maximum Output Current Boostrap Voltage Boostrap Operating Voltage Input Voltage at Pins 4, 12 Reset Output Voltage Reset Output Sink Current Input Voltage at Pin 2, 7, 9, 10 Reset Delay Sink Current Error Amplifier Output Sink Current Soft Start Sink Current Total Power Dissipation at TPINS 90C at Tamb = 70C (No copper area on PCB) Junction and Storage Temperature P a r am e t e r Value 55 50 -1 -5 Internally Limited 65 V11 + 15 12 50 50 7 30 1 30 5 1.3 -40 to 150 Unit V V V V V V V V mA V mA A mA W W C
PIN CONNECTION (top view)
T H ER M A L DATA
Symbol Rth j-pins Rth j-amb P a r am e t er Thermal Resistance Junction-Pins Thermal Resistance Junction-ambient max max V a lu e 12 60 U ni t C/W C/W
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PIN FUNCTIONS
No 1 2 3 4 Name BOOTSTRAP RESET DELAY RESET OUT RESET INPUT F u n ct i o n A Cboot capacitor connected between this terminal and the output allows to drive properly the internal D-MOS transistor. A Cd capacitor connected between this terminal and ground determines the reset signal delay time. Open Collector Reset/power Fail Signal Output. This output is high when the supply and the output voltages are safe. Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a divider to the input for power fail function. It must be connected to the pin 14 an external 30K resistor when power fail signal not required. Common Ground Terminal A series RC network connected between this terminal and ground determines the regulation loop gain characteristics. Soft Start Time Constant. A capacitor is connected between thi sterminal and ground to define the soft start time constant. The Feedback Terminal of the Regulation Loop. The output is connected directly to this terminal for 5.1V operation; It is connected via a divider for higher voltages. Multiple L4974A's are synchronized by connecting pin 10 inputs together or via an external syncr. pulse. Unregulated Input Voltage. Not Connected. 5.1V Vref Device Reference Voltage. Internal Start-up Circuit to Drive the Power Stage. Rosc. External resistor connected to ground determines the constant charging current of Cosc. Cosc. External capacitor connected to ground determines (with Rosc) the switching frequency. Regulator Output.
5, 6 15, 16 7 8 9 10 11 12, 19 13 14 17 18 20
GROUND FREQUENCY COMPENSATION SOFT START FEEDBACK INPUT SYNC INPUT SUPPLY VOLTAGE N.C. Vref Vstart OSCILLATOR OSCILLATOR OUTPUT
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C I R C U I T OPERATION The L4974A is a 3.5A monolithic stepdown switching regulator working in continuous mode realized in the new BCD Technology. This technology allows the integration of isolated vertical DMOS power transistors plus mixed CMOS/Bipolar transistors. The device can deliver 3.5A at an output voltage adjustable from 5.1V to 40V and contains diagnostic and control functions that make it particularly suitable for microprocessor based systems. BLOCK DIAGRAM The block diagram shows the DMOS power transistors and the PWM control loop. Integrated functions include a reference voltage trimmed to 5.1V 2%, soft start, undervoltage lockout, oscillator with feedforward control, pulse by pulse current limit, thermal shutdown and finally the reset and power fail circuit. The reset and power fail circuit provides an output signal for a microprocessor indicating the status of the system. Device turn on is around 11V with a typical 1V hysterysis, this threshold porvides a correct voltage for the driving stage of the DMOS gate and the hysterysis prevents instabilities. An external bootstrap capacitor charge to 12V by an internal voltage reference is needed to provide correct gate drive to the power DMOS. The driving circuit is able to source and sink peak currents of around 0.5A to the gate of the DMOS transistor. A typical switching time of the current in the DMOS transistor is 50ns. Due to the fast commutation switching frequencies up to 200kHz are possible. The PWM control loop consists of a sawtooth oscillator, error amplifier, comparator, latch and the output stage. An error signal is produced by comparing the output voltage with the precise 5.1V 2% on chip reference. This error signal is then compared with the sawtooth oscillator in order to generate frixed frequency pulse width modulated drive for the output stage. A PWM latch is included to eliminate multiple pulsing within a period even in noisy environments. The gain and stability of the loop can be adjusted by
an external RC network connected to the output of the error amplifier. A voltage feedforward control has been added to the oscillator, this maintains superior line regulation over a wide input voltage range. Closing the loop directly gives an output voltage of 5.1V, higher voltages are obtained by inserting a voltage divider. At turn on, output overcurrents are prevented by the soft start function (fig. 2). The error amplifier is initially clamped by an external capacitor, Css, and allowed to rise linearly under the charge of an internal constant current source. Output overload protection is provided by a current limit circuit. The load current is sensed by a internal metal resistor connected to a comparator. When the load current exceeds a preset threshold, the output of the comparator sets a flip flop which turns off the power DMOS. The next clock pulse, from an internal 40kHz oscillator, will reset the flip flop and the power DMOS will again conduct. This current protection method, ensures a constant current output when the system is overloaded or short circuited and limits the switching frequency, in this condition, to 40kHz. The Reset and Power fail circuit (fig. 4), generates an output signal when the supply voltage exceeds a threshold programmed by an external voltage divider. The reset signal, is generated with a delay time programmed by a external capacitor on the delay pin. When the supply voltage falls below the threshold or the output voltage goes below 5V, the reset output goes low immediately. The reset output is an open drain. Fig. 4A shows the case when the supply voltage is higher than the threshold, but the output voltage is not yet 5V. Fig. 4B shows the case when the output is 5.1V, but the supply voltage is not yet higher than the fixed threshold. The thermal protection disables circuit operation when the junction temperature reaches about 150C and has a hysterysis to prevent unstable conditions.
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Figure 1 : Feedforward Waveform.
Figure 2 : Soft Start Function.
Figure 3 : Limiting Current Function.
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Figure 4 : Reset and Power Fail Functions. A
B
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ELECTRICAL CHARACTERISTICS (refer to the test circuit, TJ = 25C, Vi = 35V, R4 = 30K, C9 = 2.7nF, fSW = 100KHz typ, unless otherwise specified) DYNAMIC CHARACTERISTICS
S y mb o l Vi Vo Vo Vo Vd I20L Pa r a m et e r Input Volt. Range (pin 11) Output Voltage Line Regulation Load Regulation Dropout Voltage between Pin 11 and 20 Max Limiting Current Efficiency T es t Conditions Vo = Vref to 40V Io = 3.5A (*) Vi =15V to 50V Io = 2A; Vo = Vref VI = 15V to 50V Io = 1A; Vo = Vref VO = Vref Io = 1A to 3.5A Io = 2A to 3A Io = 2A Io = 3.5A Vi = 15V to 50V Vo = Vref to 40V Io = 3.5A, f = 100KHz Vo = Vref Vo = 12V Vi = 2VRMS; Io = 5A f = 100Hz; Vo = Vref of Vi = 15V to 45V 4 Min. 15 5 5.1 12 8 4 0.25 0.45 4.75 T yp . M a x. 50 5.2 30 25 10 0.4 0.7 5.5 U ni t V V mV mV mV V A Fig. 5 5
80 56 90
85 90 60 100 2 110 6
% % dB KHz % 5 5 5
SVR f f/Vi
Supply Voltage Ripple Rejection Switching Frequency Voltage Stability Switching Frequency Temperature Stability of Switching Frequency Maximum Operating Switching Frequency
f/Tj fmax
Tj = 0 to 125C Vo = Vref R4 = 15K Io = 3.5A C9 = 2.2nF 200
1
% KHz
5 5
(*) Pulse testing with a low duty cycle
Vref SECTION (pin 13)
S y mb o l V13 V13 V13 V13 T I13 short Pa r a m et e r Reference Voltage Line Regulation Load Regulation Vi = 15V to 50V I13 = 0 to 1mA T e s t Condition Min. 5 T yp . 5.1 10 20 0.4 M a x. 5.2 25 40 U ni t V mV mV mV/C Fig. 7 7 7 7
Average Temperature Tj = 0C to 125C Coefficient Reference Voltage Short Circuit Current Limit V13 = 0
70
mA
7
VSTART SECTION (pin 15)
S y mb o l V14 V14 V14 I14 short Pa r a m et e r Reference Voltage Line Regulation Load Regulation Short Circuit Current Limit Vi = 15 to 50V I14 = 0 to 1mA V15 = 0V T e s t Condition Min. 11.4 T yp . 12 0.6 50 80 M a x. 12.6 1.4 200 U ni t V V mV mA Fig. 7 7 7 7
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ELECTRICAL CHARACTERISTICS (continued) DC CHARACTERISTICS
S y mb o l V11on V11 Hyst I11Q I11OQ I20L Pa r a m et e r Turn-on Threshold Turn-off Hysteresys Quiescent Current Operating Supply Current Out Leak Current V8 = 0; S1 = D V8 = 0; S1 = B; S2 = B Vi = 55V; S3 = A; V8 = 0 T e s t Condition Min. 10 T yp . 11 1 13 16 19 23 2 M ax . 12 Unit V V mA mA mA Fig. 7A 7A 7A 7A 7A
SOFT START (pin 8)
S y mb o l I8 V8 Pa r a m et e r Soft Start Source Current Output Saturation Voltage T e s t Condition V8 = 3V; V9 = 0V I8 = 20mA; V11 = 10V I8 = 200A; V11 = 10V Min. 80 T yp . 115 M ax . 150 1 0.7 Unit A V V Fig. 7B 7B 7B
ERROR AMPLIFIER
S y mb o l V7H V7L I7H -I7L I9 GV SVR VOS Pa r a m et e r High Level Out Voltage Low Level Out Voltage Source Output Current Sink Output Current Input Bias Current DC Open Loop Gain Supply Voltage Rejection Input Offset Voltage T e s t Condition I7 = -100A; S1 = C V9 = 4.7V I7 = 100A; S1 = C V9 = 5.3V; V7 = 1V; V7 = 4.7V V7 = 6V; V9 = 5.3V S1 = B; RS = 10K S1 = A; RS = 10 15 < Vi < 50V RS = 50 S1 = A 60 60 80 2 10 100 100 150 150 0.4 3 Min. 6 1.2 T yp . M ax . Unit V V A A A dB dB mV Fig. 7C 7C 7C 7C 7C 7C 7C 7C
RAMP GENERATOR (pin 18)
S y mb o l V18 V18 I18 I18 Pa r a m et e r Ramp Valley Ramp Peak Min. Ramp Current Max. Ramp Current T e s t Condition S1 = B; S2 = B S1 = B Vi = 15V S2 = B Vi = 45V S1 = A; I17 = 100A S1 = A; I17 = 1mA 2.4 Min. 1.2 T yp . 1.5 2.5 5.5 270 2.7 M ax . Unit V V V A mA Fig. 7A 7A 7A 7A 7A
300
SYNC FUNCTION (pin 10)
S y mb o l V10 V10 +I10L +I10H V10 tW Pa r a m et e r Low Input Voltage High Input voltage T e s t Condition Vi = 15V to 50V; V8 = 0; S1 = B; S2 = B; S4 = B V8 = 0; S1 = B; S2 = B; S4 = B Min. 0.3 2.5 T yp . M ax . 0.9 5.5 0.4 1.5 4 0.3 5 0.5 0.8 Unit V V mA mA V s Fig. 7A 7A 7A 7A
Sync Input Current with Low V10 = V18 = 0.9V; S4 = B; Input Voltage S1 = B; S2 = B Input Current with High V10 = 2.5V Input Voltage Output Amplitude Output Pulse Width Vthr = 2.5V
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EL EC T R I C A L CHARACTERISTICS (continued) RESET AND POWER FAIL FUNCTIONS
S y mb o l V9R V9F V2H V2L I2SO I2SI V3S I3 V4R V4H I4 Pa r a m et e r Rising Thereshold Voltage (pin 9) Falling Thereshold Voltage (pin 9) Delay High Threshold Volt. Delay Low Threshold Volt. Delay Source Current Delay Source Sink Current Output Saturation Voltage Output Leak Current Rising Threshold Voltage Hysteresis Input Bias Current T es t Conditions Vi = 15 to 50V V4 = 5.3V Vi = 15 to 50V V4 = 5.3V Vi = 15 to 50V V4 = 5.3V V9 = V13 Vi = 15 to 50V V4 = 4.7V V9 = V13 V4 = 5.3V; V2 = 3V V4 = 4.7V; V2 = 3V I3 = 15mA; S1 = B V4 = 4.7V V3 = 50V; S1 = A V9 = V13 4.955 0.4 5.1 0.5 1 Min. Vref -130 4.77 4.95 1 30 10 0.4 100 5.25 0.6 3 T yp . Vref -100 Vref -200 5.1 1.1 60 M a x. Vref -80 Vref -160 5.25 1.2 80 U ni t V mV V mV V V A mA V A V V A Fig. 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D
Figure 5 : Test and Evaluation Board Circuit.
TYPICAL PERFORMANCES (using evaluation board) : n = 83% (Vi = 35V ; Vo = VREF ; Io = 3.5A ; fsw = 100KHz) Vo RIPPLE = 30mV (at 1A) Line regulation = 12mV (Vi = 15 to 50V) Load regulation = 8mV (Io = 1 to 3.5A) for component values Refer to the fig. 5 (Part list).
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Figure 6a : Component Layout of fig.5 (1 : 1 scale). Evaluation Board Available
PART LIST
R1 = 30K R2 = 10K R3 = 15K R4 = 30K R5 = 22 R6 = 4.7K R7 = see table A R8 = OPTION R9 = 4.7K * C1 = C2 = 1000F 63V EYF (ROE) C3 = C4 = C5 = C6 = 2,2F 50V C7 = 390pF Film C8 = 22nF MKT 1837 (ERO) C9 = 2.7nF KP 1830 (ERO) C10 = 0.33F Film C11 = 1nF ** C12 = C13 = C14 = 100F 40V EKR (ROE) C15 = 1F Film D1 = SB 560 (OR EQUIVALENT) L1 = 150H core 58310 MAGNETICS 45 TURNS 0.91mm (AWG 19) COGEMA 949181
* 2 capacitors in parallel to increase input RMS current capability. * * 3 capacitors in parallel to reduce total output ESR.
Table A
V0 12V 15V 18V 24V R9 4.7k 4.7k 4.7k 4.7k R7 6.2kW 9.1k 12 18
Table B SUGGESTED BOOSTRAP CAPACITORS
Op e r a t in g Frequency f = 20KHz f = 50KHz f = 100KHz f = 200KHz f = 500KHz B o o s t ra p Cap.c10 680nF 470nF 330nF 220nF 100nF
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Figure 6b: P.C. Board and Component Layout of the Circuit of Fig. 5. (1:1 scale)
Figure 7 : DC Test Circuits.
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Figure 7A.
Figure 7B.
Figure 7C.
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Figure 7D.
Figure 8 : Quiescent Drain Current vs. Supply Voltage (0% duty cycle - see fig. 7A).
Figure 9 : Quiescent Drain Current vs. Junction Temperature (0% duty cycle).
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Figure 10 : Quiescent Drain Current vs. Duty Cycle. Figure 11 : Reference Voltage (pin 13) vs. Vi (see fig. 7).
Figure 12 : Reference Voltage (pin 13) vs. Junction Temperature (see fig. 7).
Figure 13 : Reference Voltage (pin 14) vs. Vi (see fig. 7).
Figure 14 : Reference Voltage (pin 14) vs. Junction Temperature (see fig. 7).
Figure 15 : Reference Voltage 5.1V (pin 13) Supply Voltage Ripple Rejection vs. FreSVR (dB)
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Figure 16 : Switching Frequency vs. Input Voltage (see fig. 5). Figure 17 : Switching Frequency vs. Junction Temperature (see fig. 5).
Figure 18 : Switching Frequency vs. R4 (see fig.5).
Figure 19 : Maximum Duty Cycle vs. Frequency.
Figure 20 : Supply Voltage Ripple Rejection vs. Frequency (see fig. 5).
Figure 21 : Efficiency vs. Output Voltage.
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Figure 22 : Line Transient Response (see fig. 5). Figure 23 : Load Transient Response (see fig. 5).
Figure 24 : Dropout Voltage between Pin 11 and Pin 20 vs. Current at Pin 20.
Figure 25 : .Dropout Voltage between Pin 11 and Pin 20 vs. Junction Temperature.
Figure 26 : Power Dissipation (device only) vs. Input Voltage.
Figure 27 : Power Dissipation (device only) vs. Input Voltage.
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Figure 28 : Power Dissipation (device only) vs. Output Voltage. Figure 29 : Power Dissipation (device only) vs. Output Voltage.
Figure 30 : Power Dissipation (device only) vs. Output Current.
Figure 31 : Power Dissipation (device only) vs. Output Current.
Figure 32 : Efficiency vs. Output Current.
Figure 33 : Test PCB Thermal Characteristic.
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Figure 34 : Junction to Ambient Thermal Resistance vs. Area on Board Heatsink (DIP 16+2+2) Figure 35: Maximum Allowable Power Dissipation vs. Ambient Temperature (Powerdip)
Figure 36: Open Loop Frequency and Phase of Error Amplifier (see fig. 7C).
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Figure 37 : 3.5A 5.1V Low Cost Application Circuit.
Figure 38 : A 5.1V/12V Multiple Supply. Note the Synchronization between the L4974A and L4970A.
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Figure 39 : L4974A's Sync. Example.
Figure 40: 1A/24V Multiple Supply. Note the synchronization between the L4974A and L4962
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mm MIN. a1 B b b1 D E e e3 F I L Z 3.30 1.27 8.80 2.54 22.86 7.10 5.10 0.130 0.38 0.51 0.85 0.50 0.50 24.80 0.346 0.100 0.900 0.280 0.201 0.015 1.40 TYP. MAX. MIN. 0.020 0.033 0.020 0.020 0.976 0.055 inch TYP. MAX.
DIM.
OUTLINE AND MECHANICAL DATA
Powerdip 20
0.050
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics Printed in Italy All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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