 DSILC6-4xx Product Page |
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The introduction of multimedia services in 3G phones is driving the increase in resolution of graphic displays and cameras. The interfaces between displays and camera modules to the base module or multimedia processor through the flex cable become tough cabling constraints and EMI becomes a key concern.
To solve these problems, several display manufacturers, semiconductor and camera module makers have developed a high speed serial bus to liberate phone designers from crowded and noisy parallel interface designs. As an example of bandwidth requirements of the serial bus, for a VGA resolution (640x480) with 18bpp (262kcolor) and 60fps, the required bandwidth is 640x480x18x60 = 330Mbps. |
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With clamshell or slide phones, ESD events can damage the ICs via the hinge of the phone. To reduce ESD susceptibility, low capacitance ESD protection must be implemented at the output of the ICs, as close as possible to the display and camera connector. The data frequency on the bus needs low capacitance ESD protection. Taking into consideration the parasitic capacitance of the cable routing, for transmission rates above 400Mbps, it is considered that the capacitance of the ESD protection should not exceed 3pF. To fully answer this need, ST has developed the DSILC6-4xx series of protection devices.
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The Benefits Of Serial Bus |
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As the resolution increases, the data bandwidth in the handsets also increases, and so does the power required. In clamshell cellphones, the major user of power in the flip is the display and camera module. To lower the power needed to transfer high bandwidth data, transforming traditional parallel interfaces to serial offers benefits such as:
 Low pin count: the serial buses can translate a wide, low-speed parallel data stream into a narrow high speed serial data stream
Reduced EMI and power consumption: I/Os are moving from a low-speed single ended technology to a high-speed differential technology, reducing EMI and power consumption
Standardized interfaces: several IC makers are promoting their own serial interface protocol. Most are based on LVDS technology
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Part number |
VF @IF = 10mA |
VRM |
VBR |
Cline @ 0 |
Package |
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1V |
5V
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6.V
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2.5pF
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SOT-666 |
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0.9V |
Flip-chip |
2.5pF max line capacitance for high speed serial interface compliance
1.25pF max line to line
4-line protection in one package for high integration
VBR = 6V
No insertion loss to 2.0GHz
Low leakage current
Flip-Chip and micro package for ultra low space
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