| Processor Architecture and Compilation |
| |  | Embedded systems have invaded our lives. From the dishwasher to the anti-lock breaking system of our cars, from cell phones to DVD players, they are everywhere.While there was a time where hand-written assembly code was the only option to program a processor, the complexity of today's application makes this reasonable only for the critical parts. (More...) | | | |
Vol. 1, No. 2, September 2004 - Table of Contents |
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| Art. 1 | A Multi-Level Computing Architecture for Embedded Multimedia Applications | by F. Karim, A. Mellan (STMicroelectronics), U. Aydonat, T. Abdelrahman, A. Nguyen (University of Toronto) | p. 4 | | Art. 2 | FlexPerf: a Performance Evaluation Framework for Embedded Software Developers and Architecture Designers | by S. De Paoli, E. Galix, M. Santana, D. Singh (STMicroelectronics) | p. 17 | | Art. 3 | Code Compression for VLIW Embedded Processors | by E. Piccinelli, R. Sannino (STMicroelectronics) | p. 32 | | Art. 4 | Balancing Code Size and Performance for ST100 Processor Cores | by M. Leair (STMicroelectronics) | p. 47 | | Art. 5 | FICO: a Fast Instruction Cache Optimizer | by M. Garatti (STMicroelectronics) | p. 56 | | Art. 6 | A Retargetable Register Allocation Framework for Embedded Processors | by J. Daveau, T. Thery, T. Lepley, M. Santana (STMicroelectronics) | p. 67 | | Art. 7 | Optimizing the Translation Out-of-SSA with Renaming Constraints | by F. de Ferrière, C. Guillon (STMicroelectronics); F. Rastello (ENS Lyon) | p. 81 | | Art. 8 | Hardware Parameters of VLIW Cores and Code Quality Factors Affecting Alias Analysis Impact | by R. Costa, M. Garatti, E. Rohou (STMicroelectronics), S. Crespi Reghizzi (Politecnico di Milano) | p. 96 | | Special Report | From Machine Scheduling to VLIW Instruction Scheduling | by Benoit Dupont de Dinechin (STMicroelectronics) | p. 1 |
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