Section
Author's Guide | Reviewer's Guide

ST Journal of Research
Processor Architecture and Compilation
for Embedded Systems

Vol. 1, No. 2, September 2004- Art. 5
 
FICO: a Fast Instruction Cache Optimizer

by
Marco Garatti (STMicroelectronics)

Copyright
© Springer Verlag, 2004 http://www.springer.de/comp/lncs/index.html

 
Abstract
This paper shows the results obtained by FICO, a tool aimed at reducing instruction cache conflict
misses. FICO reorders functions without requiring any program execution to gather profiling information. The control flow graph annotated with estimated execution frequencies is the actual input of the algorithm.
The tool has been implemented as a pre-linking phase in a newly developed state-of-the-art commercial-quality compiler co-designed by STMicroelectronics and Hewlett-Packard for their embedded processor family LX. Experimental results show that FICO can provide a speed-up of about 8% on embedded applications.
 

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