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SPD for DRAM Modules
2 Kbit serial presence detect (SPD) EEPROM for double data rate (DDR1 and DDR2) DRAM modules
Datasheet
Format:
(279 kb)
or
(48 kb)
Last Updated: 19/03/2009
Pages: 33
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EEPROM Information Pages
EEPROM, Serial Product Pages
Related Press Releases
New Serial Presence Detect (SPD) EEPROM from STMicroelectronics Fully Supports JEDEC DDR2 Standard
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M34E02
2 Kbit serial presence detect (SPD) EEPROM for double data rate (DDR1 and DDR2) DRAM modules
Features
2 Kbit EEPROM for DDR1 and DDR2 serial presence detect Backward compatible with the M34C02 Permanent and reversible software data protection for lower 128 bytes 100 kHz and 400 kHz I2C bus serial interface Single supply voltage: 1.7 V to 5.5 V Byte and Page Write (up to 16 bytes) Self-timed write cycle Noise filtering Schmitt trigger on bus inputs Noise filter on bus inputs Enhanced ESD/latch-up protection More than 1 Million erase/write cycles More than 40 years' data retention ECOPACK (RoHS compliant) packages TSSOP8 (DW) 4.4 × 3 mm UFDFPN8 (MB) 2 × 3 mm (MLP)
March 2009
Rev 7
1/33
www.st.com 1
Contents
M34E02
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 2.5 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5.1 2.5.2 2.5.3 2.5.4 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 3.2 3.3 3.4 3.5 3.6 Star t condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Setting the write-protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6.1 3.6.2 SWP and CWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PSWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7.1 3.7.2 3.7.3 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . 16
3.8
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8.1 3.8.2 3.8.3 3.8.4 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/33
M34E02
Contents
5
Use within a DDR1/DDR2 DRAM module . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 Programming the M34E02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.1 5.1.2 Isolated DRAM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DRAM module inserted in the application motherboard . . . . . . . . . . . . 19
6 7 8 9 10
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3/33
List of tables
M34E02
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DRAM DIMM connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Acknowledge when writing data or defining the write-protection (instructions with R/W bit = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Acknowledge when reading the write protection (instructions with R/W bit = 1). . . . . . . . . 20 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Operating conditions (for temperature range 1 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operating conditions (for temperature range 6 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC characteristics (for temperature range 1 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC characteristics (for temperature range 6 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 × 3 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 TSSOP8 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 29 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4/33
M34E02
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TSSOP and MLP connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Maximum RP value versus bus parasitic capacitance (C) for an I2C bus . . . . . . . . . . . . . . . 9 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Result of setting the write protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Setting the write protection (WC = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write mode sequences in a non write-protected area . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Serial presence detect block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 × 3 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 TSSOP8 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 29
5/33
Description
M34E02
1
Description
The M34E02 is a 2 Kbit serial EEPROM memory able to lock permanently the data in its first half (from location 00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs (dual interline memory modules) with serial presence detect (SPD). All the information concerning the DDR1 or DDR2 configuration of the DRAM module (such as its access speed, size and organization) can be kept write-protected in the first half of the memory. The first half of the memory area can be write-protected using two different software write protection mechanisms. By sending the device a specific sequence, the first 128 bytes of the memory become write protected: permanently or resettable. In addition, the device allows the entire memory area to be write protected, using the WC input (for example by tieing this input to VCC). These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 256 × 8 bits. I2C uses a two wire serial interface, comprising a bi-directional data line and a clock line. The device carries a built-in 4-bit device type identifier code (1010) in accordance with the I2C bus definition to access the memory area and a second device type identifier code (0110) to define the protection. These codes are used together with the voltage level applied on the three chip enable inputs (E2, E1, E0). The device behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a device select code and RW bit (as described in Table 2), terminated by an acknowledge bit. When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for WRITE, and after a NoAck for READ. Figure 1. Logic diagram
VCC
3 E0-E2 SCL WC M34E02 SDA
VSS
AI09020
6/33
M34E02 Figure 2. TSSOP and MLP connections (top view)
M34E02 E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI09021
Description
VCC WC SCL SDA
1. See the Package mechanical data section for package dimensions, and how to identify pin-1.
Table 1.
Signal names
Signal names Description Chip Enable Serial Data Serial Clock Write Control Supply voltage Ground
E0, E1, E2 SDA SCL WC VCC VSS
7/33
Signal description
M34E02
2
2.1
Signal description
Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.
2.2
Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated).
2.3
Chip Enable (E0, E1, E2)
These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. In the end application, E0, E1 and E2 must be directly (not through a pull-up or pull-down resistor) connected to VCC or VSS to establish the device select code. When these inputs are not connected, an internal pulldown circuitry makes (E0,E1,E2) = (0,0,0). The E0 input is used to detect the VHV voltage, when decoding an SWP or CWP instruction. Figure 3. Device select code
VCC VCC
M34E02 Ei
M34E02 Ei
VSS
VSS
Ai12301
2.4
Write Control (WC)
This input signal is provided for protecting the contents of the whole memory from inadvertent write operations. Write Control (WC) is used to enable (when driven low) or disable (when driven high) write instructions to the entire memory area or to the Protection Register. When Write Control (WC) is tied low or left unconnected, the write protection of the first half of the memory is determined by the status of the Protection Register.
8/33
M34E02
Signal description
2.5
2.5.1
Supply voltage (VCC)
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 8). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW).
2.5.2
Power-up conditions
When the power supply is turned on, VCC rises from VSS to VCC. The VCC rise time must not vary faster than 1 V/s.
2.5.3
Device reset
In order to prevent inadvertent write operations during power-up, a power-on reset (POR) circuit is included. At power-up (continuous rise of VCC), the device does not respond to any instruction until VCC reaches the power-on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 8). When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode. However, the device must not be accessed until VCC has reached a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range. In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops below the power-on reset threshold voltage, the device stops responding to any instruction sent to it.
2.5.4
Power-down conditions
During power-down (continuous decrease in VCC), the device must be in Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress). Figure 4.
Bus line pull-up resistor (k )
100
fC = 400 kHz, tLOW = 1.3 s Rbus x Cbus time c ons tant must be less than 500 ns
Maximum RP value versus bus parasitic capacitance (C) for an I2C bus
VCC
10
Rbus I²C bus master SCL SDA
M24xxx
1 10 100 Bus line capacitor (pF) 1000
Cbus
ai14796
9/33
Signal description Figure 5. I2C bus protocol
M34E02
SCL
SDA SDA Input SDA Change
Start condition
Stop condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
Start condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK Stop condition
AI00792c
Table 2.
Device select code
Chip Enable signals Device type identifier b7(1) 1 b6 0 b5 1 b4 0 Chip Enable bits b3 E2 0 0 0 1 1 0 E2 0 0 E2 b2 E1 0 1 E1 0 1 E1 b1 E0 1 1 E0 1 1 E0 RW b0 RW 0 0 0 1 1 1
Memory area select code (two arrays)(2) Set write protection (SWP) Clear write protection (CWP) Permanently set write protection (PSWP)(2) Read SWP Read CWP Read PSWP
(2)
E2 VSS VSS E2 VSS VSS E2
E1
E0
VSS VHV(3) VCC VHV(3) E1 E0
VSS VHV(3) VCC E1 VHV(3) E0
1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. 3. VHV is defined in Table 13.
10/33
M34E02
Device operation
3
Device operation
The device supports the I2C protocol. This is summarized in Figure 5 Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The memory device is always a slave in all communication.
3.1
Start condition
Star t is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given.
3.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle.
3.3
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits.
3.4
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low.
11/33
Device operation
M34E02
3.5
Memory addressing
To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (on Serial Data (SDA), most significant bit first). The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable "Address" (E2, E1, E0). To address the memory array, the 4-bit device type identifier is 1010b; to access the write-protection settings, it is 0110b. Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the device select code is received, the device only responds if the Chip Enable address is the same as the value on the Chip Enable (E0, E1, E2) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the device select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into Standby mode. Table 3. Operating modes
Mode Current Address Read Random Address Read 1 Sequential Read Byte Write Page Write
1. X = VIH or VIL.
RW bit 1 0
WC(1) X X
Bytes 1 1
Initial Sequence Star t, Device Select, RW = 1 Star t, Device Select, RW = 0, Address reStar t, Device Select, RW = 1
X X VIL VIL 1 1 16
1 0 0
Similar to Current or Random Address Read Star t, Device Select, RW = 0 Star t, Device Select, RW = 0
Figure 6.
Result of setting the write protection
FFh Standard Array Memory Area Standard Array 00h Default EEPROM memory area state before write access to the Protect Register 80h 7Fh Standard Array Write Protected Array
FFh
80h 7Fh
00h
State of the EEPROM memory area after write access to the Protect Register
AI01936C
12/33
M34E02
Device operation
3.6
Setting the write-protection
The M34E02 has a hardware write-protection feature, using the Write Control (WC) signal. This signal can be driven high or low, and must be held constant for the whole instruction sequence. When Write Control (WC) is held high, the whole memory array (addresses 00h to FFh) is write protected. When Write Control (WC) is held low, the write protection of the memory array is dependent on whether software write-protection has been set. Software write-protection allows the bottom half of the memory area (addresses 00h to 7Fh) to be write protected irrespective of subsequent states of the Write Control (WC) signal. Software write-protection is handled by three instructions:
SWP: Set Write Protection CWP: Clear Write Protection PSWP: Permanently Set Write Protection
The level of write-protection (set or cleared) that has been defined using these instructions, remains defined even after a power cycle.
3.6.1
SWP and CWP
If the software write-protection has been set with the SWP instruction, it can be cleared again with a CWP instruction. The two instructions (SWP and CWP) have the same format as a Byte Write instruction, but with a different device type identifier (as shown in Table 2). Like the Byte Write instruction, it is followed by an address byte and a data byte, but in this case the contents are all "Don't Care" (Figure 7). Another difference is that the voltage, VHV, must be applied on the E0 pin, and specific logical levels must be applied on the other two (E1 and E2, as shown in Table 2).
3.6.2
PSWP
If the software write-protection has been set with the PSWP instruction, the first 128 bytes of the memory are permanently write-protected. This write-protection cannot be cleared by any instruction, or by power-cycling the device, and regardless the state of Write Control (WC). Also, once the PSWP instruction has been successfully executed, the M34E02 no longer acknowledges any instruction (with a device type identifier of 0110) to access the write-protection settings. Figure 7. Setting the write protection (WC = 0)
START
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY
CONTROL BYTE
WORD ADDRESS
DATA
ACK
ACK
ACK
VALUE VALUE (DON'T CARE) (DON'T CARE)
AI01935B
STOP
13/33
Device operation
M34E02
3.7
Write operations
Following a Start condition the bus master sends a device select code with the RW bit reset to 0. The device acknowledges this, as shown in Figure 8, and waits for an address byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte. When the bus master generates a Stop condition immediately after the Ack bit (in the "10th bit" time slot), either at the end of a Byte Write or a Page Write, the internal memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and the device does not respond to any requests.
3.7.1
Byte Write
After the device select code and the address byte, the bus master sends one data byte. If the addressed location is hardware write-protected, the device replies to the data byte with NoAck, and the location is not modified. If, instead, the addressed location is not Writeprotected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 8
3.7.2
Page Write
The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the page, a condition known as `roll-over' occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if Write Control (WC) is low. If the addressed location is hardware write-protected, the device replies to the data byte with NoAck, and the locations are not modified. After each byte is transferred, the internal byte address counter (the 4 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition.
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M34E02 Figure 8. Write mode sequences in a non write-protected area
ACK Byte Write Device select Start R/W ACK Page Write Device select Start R/W ACK Data in N Stop ACK ACK Data in 1 ACK Data in Stop ACK Byte address ACK
Device operation
Byte address
Data in 2
AI01941b
Figure 9.
Write cycle polling flowchart using ACK
WRITE cycle in progress
Start condition Device select with RW = 0
NO First byte of instruction with RW = 0 already decoded by the device
ACK returned YES
NO
Next operation is addressing the memory
YES
ReStart
Send address and receive ACK
Stop
NO
Start condition
YES
Data for the WRITE operation
Device select with RW = 1
Continue the WRITE operation
Continue the Random READ operation
AI01847d
15/33
Device operation
M34E02
3.7.3
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in Table 14, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 9, is:
Initial condition: a Write cycle is in progress. Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction). Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).
3.8
Read operations
Read operations are performed independently of whether hardware or software protection has been set. The device has an internal address counter which is incremented each time a byte is read.
3.8.1
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition.
3.8.2
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the RW bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 10, without acknowledging the byte.
3.8.3
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter `rolls-over', and the device continues to output data from memory address 00h.
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M34E02
Device operation
3.8.4
Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) low during this time, the device terminates the data transfer and switches to its Standby mode. Figure 10. Read mode sequences
ACK Current Address Read Start Dev select R/W Data out Stop ACK Dev select * Start R/W NO ACK
ACK Random Address Read Start Dev select * R/W
ACK Data out
NO ACK
Byte address
ACK Sequential Current Read Start Dev select R/W Data out 1
ACK
ACK
NO ACK Data out N Stop
ACK Sequential Random Read Start Dev select * R/W
ACK Dev select * Start
ACK Data out 1 R/W
ACK
Byte address
ACK
NO ACK Data out N Stop
1. The seven most significant bits of the device select code of a Random Read (in the 1st and 3rd bytes) must be identical.
Stop
AI01942b
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Initial delivery state
M34E02
4
Initial delivery state
The device is delivered with all bits in the memory array set to `1' (each Byte contains FFh).
5
Use within a DDR1/DDR2 DRAM module
In the application, the M34E02 is soldered directly in the printed circuit module. The three Chip Enable inputs (E0, E1, E2) must be connected to VSS or VCC directly (that is without using a pull-up or pull-down resistor) through the DIMM socket (see Table 4). The pull-up resistors needed for normal behavior of the I2C bus are connected on the I2C bus of the mother-board (as shown in Figure 11). The Write Control (WC) of the M34E02 can be left unconnected. However, connecting it to VSS is recommended, to maintain full read and write access. Table 4. DRAM DIMM connections
DIMM position 0 1 2 3 4 5 6 7 E2 VSS VSS VSS VSS VCC VCC VCC VCC E1 VSS VSS VCC VCC VSS VSS VCC VCC E0 VSS VCC VSS VCC VSS VCC VSS VCC
5.1
Programming the M34E02
The situations in which the M34E02 is programmed can be considered under two headings:
when the DDR2 DRAM is isolated (not inserted on the PCB motherboard) when the DDR2 DRAM is inserted on the PCB motherboard
5.1.1
Isolated DRAM module
With specific programming equipment, it is possible to define the M34E02 content, using Byte and Page Write instructions, and its write-protection using the SWP and CWP instructions. To issue the SWP and CWP instructions, the DRAM module must be inserted in a specific slot where the E0 signal can be driven to VHV during the whole instruction. This programming step is mainly intended for use by DRAM module makers, whose end application manufacturers will want to clear this write-protection with the CWP on their own specific programming equipment, to modify the lower 128 Bytes, and finally to set permanently the write-protection with the PSWP instruction.
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M34E02
Use within a DDR1/DDR2 DRAM module
5.1.2
DRAM module inserted in the application motherboard
As the final application cannot drive the E0 pin to VHV, the only possible action is to freeze the write-protection with the PSWP instruction. Table 5 and Table 6 show how the Ack bits can be used to identify the write-protection status. Table 5. Acknowledge when writing data or defining the write-protection (instructions with R/W bit = 0)
WC input level Instruction PSWP, SWP or CWP X Page or Byte Write in lower 128 bytes SWP CWP 0 PSWP Page or Byte Write in lower 128 bytes SWP 1 CWP PSWP Page or Byte Write 0 Not Protected 1 PSWP, SWP or CWP Page or Byte Write PSWP, SWP or CWP Page or Byte Write Ack NoAck Ack Ack Ack NoAck Ack Ack Ack Ack Ack Ack Ack Address Ack Data NoAck No No Yes Yes No No No No No Yes Yes No No Ack Address Ack Data byte Ack Write cycle (tW) No
Status
NoAck
Permanently protected
Not Not NoAck NoAck significant significant
Not Not NoAck NoAck significant significant Not significant Not significant Address Ack Ack Ack Not significant Not significant Data Ack Ack NoAck
Protected with SWP
Not Not NoAck NoAck significant significant Not significant Not significant Address Not significant Address Not significant Address Ack Ack Ack Ack Ack Ack Ack Not NoAck significant Not NoAck significant Data Not significant Data NoAck Ack Ack
Not NoAck significant Data NoAck
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Use within a DDR1/DDR2 DRAM module Table 6.
Status Permanently protected Protected with SWP Not protected
M 34E02
Acknowledge when reading the write protection (instructions with R/W bit = 1)
Instruction PSWP, SWP or CWP SWP CWP PSWP PSWP, SWP or CWP Ack NoAck NoAck Ack Ack Ack Address Not significant Not significant Not significant Not significant Not significant Ack NoAck NoAck NoAck NoAck NoAck Data byte Not significant Not significant Not significant Not significant Not significant Ack NoAck NoAck NoAck NoAck NoAck
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M34E02
Use within a DDR1/DDR2 DRAM module Figure 11. Serial presence detect block diagram
DRAM module slot number 7 E2
R = 4.7 k E1 VCC E0 SCL SDA
DRAM module slot number 6 E2
E1
E0
SCL SDA
VCC DRAM module slot number 5 E2
VSS
E1
E0
SCL SDA
VCC VSS VCC DRAM module slot number 4 E2 VCC DRAM module slot number 3 E2 VSS DRAM module slot number 2 E2
E1
E0 VSS
SCL SDA
E1
E0 VCC
SCL SDA
E1
E0
SCL SDA
VSS VCC VSS DRAM module slot number 1 E2 VSS DRAM module slot number 0 E2 E1 E0 VCC SCL SDA
E1
E0
SCL SDA
VSS SCL line SDA line From the motherboard I2C master controller
AI01937b
1. E0, E1 and E2 are wired at each DRAM module slot in a binary sequence for a maximum of 8 devices. 2. Common clock and common data are shared across all the devices.
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Maximum rating
M34E02
6
Maximum rating
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 7.
Symbol TSTG VIO IOL VCC VESD Storage temperature Input or output range DC output current (SDA = 0) Supply voltage Electrostatic discharge voltage (human body model)(1) E0 Others
Absolute maximum ratings
Parameter Min. 65 0.50 0.50 0.5 4000 Max. 150 10.0 6.5 5 6.5 4000 Unit C V mA V V
1. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
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M34E02
DC and AC parameters
7
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 8.
Symbol VCC TA Supply voltage Ambient operating temperature
Operating conditions (for temperature range 1 devices)
Parameter Min. 1.7 0 Max. 3.6 70 Unit V C
Table 9.
Symbol VCC TA
Operating conditions (for temperature range 6 devices)
Parameter Supply voltage Ambient operating temperature Min. 1.7 40 Max. 5.5 +85 Unit V C
Table 10.
Symbol CL
AC measurement conditions
Parameter Load capacitance Input rise and fall times Input levels Input and output timing reference levels Min. 100 50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V
Figure 12. AC measurement I/O waveform
Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
23/33
DC and AC parameters Table 11.
Symbol CIN CIN ZEiL ZEiH ZWCL ZWCH tNS
M34E02 Input parameters
Parameter(1) Test condition Min. Ma x . 8 6 VIN < 0.3VCC VIN > 0.7VCC VIN < 0.3VCC VIN > 0.7VCC 30 800 5 500 200 Unit pF pF k k k k ns
Input capacitance (SDA) Input capacitance (other pins) Ei (E0, E1, E2) input impedance Ei (E0, E1, E2) input impedance WC input impedance WC input impedance Pulse width ignored (input filter on SCL and SDA)
1. Characterized, not tested in production.
Table 12.
Symbol ILI ILO
DC characteristics (for temperature range 1 devices)
Parameter Input leakage current (SCL, SDA) Output leakage current Test condition (in addition to those in Table 8) VIN = VSS or VCC VOUT = VSS or VCC, SDA in Hi-Z VCC = 1.7 V, fc = 100 kHz (rise/fall time < 30 ns) Min M ax 2 2 1 2 2 1 0.45 0.45 0.7VCC VHV VCC 4.8 V IOL = 2.1 mA, 2.2 V VCC 3.6 V IOL = 0.7 mA, VCC = 1.7 V 7 0.3 VCC 0.25VCC VCC+1 10 0.4 0.2 Unit A A mA mA A A V V V V V V
ICC
Supply current (read) VCC = 3.6 V, fc = 100 kHz (rise/fall time < 30 ns) Standby supply current Input low voltage (SCL, SDA, WC) Input high voltage (SCL, SDA, WC) E0 high voltage Output low voltage VIN = VSS or VCC, VCC = 3.6 V VIN = VSS or VCC, VCC = 1.7 V 2.5 VCC 1.8 V VCC < 2.5 V
ICC1
VIL VIH VHV VOL
24/33
M34E02 Table 13.
Symbol ILI ILO
DC and AC parameters DC characteristics (for temperature range 6 devices)
Parameter Input leakage current (SCL, SDA) Output leakage current Test condition (in addition to those in Table 9) VIN = VSS or VCC SDA in Hi-Z, external voltage applied on SDA: VSS or VCC VCC < 2.5 V, fc = 400 kHz (rise/fall time < 50 ns) ICC Supply current (read) VCC 2.5 V, fc = 400 kHz (rise/fall time < 50 ns) Device not selected(1), VIN = VSS or VCC, VCC 2.5 V Device not selected(1), VIN = VSS or VCC, VCC < 2.5 V 2.5 VCC 1.8 V VCC < 2.5 V 0.45 0.45 0.7VCC VHV VCC 4.8 V IOL = 3.0 mA, VCC = 5.5 V VOL Output low voltage IOL = 2.1 mA, VCC = 2.5 V IOL = 0.7 mA, VCC = 1.7 V 7 Min M ax 2 2 1 3 2 1 0.3 VCC 0.25VCC VCC+1 10 0.4 0.4 0.2 Unit A A mA mA A A V V V V V V V
ICC1
Standby supply current
VIL VIH VHV
Input low voltage (SCL, SDA, WC) Input high voltage (SCL, SDA, WC) E0 high voltage
1. The device is not selected after a power-up, after a read command (after the Stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a write command).
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DC and AC parameters Table 14. AC characteristics
Test conditions specified in Table 10, Table 8 and Table 9 Symbol fC tCHCL tCLCH tDL1DL2(1) tXH1XH2(2) tXL1XL2(2) tDXCX tCLDX tCLQX tCLQV(3) tCHDL(4) tDLCL tCHDH tDHDL tW Alt. fSCL tHIGH tLOW tF tR tF tSU:DAT tHD:DAT tDH tAA tSU:STA tHD:STA tSU:STO tBUF tWR Clock frequency Clock pulse width high Clock pulse width low SDA (out) fall time Input signal rise time Input signal fall time Data in set up time Data in hold time Data out hold time Clock low to next data valid (access time) Star t condition setup time Star t condition hold time Stop condition setup time Time between Stop condition and next Start condition Write time 600 1300 20 20 20 100 0 200 200 600 600 600 1300 5 900 100 300 300 Parameter Min. Max. 400
M34E02
Unit kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ms
1. Sampled only, not 100% tested. 2. Values recommended by I²C-bus/Fast-Mode specification. 3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 4. For a re-Start condition, or following a Write cycle.
26/33
M34E02 Figure 13. AC waveforms
tXL1XL2 tXH1XH2 SCL tDLCL SDA In tCHDX Start condition tXH1XH2 SDA Input tCLDX SDA tDXCX Change tXL1XL2 tCHCL tCLCH
DC and AC parameters
tCHDH tDHDL Start Stop condition condition
SCL
SDA In tW tCHDH Stop condition Write cycle tCHDX Start condition
tCHCL SCL tCLQV SDA Out Data valid tCLQX Data valid
AI00795e
tDL1DL2
27/33
Package mechanical data
M34E02
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 14. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 × 3 mm, package outline
D L3 e b L1
E
E2
L A D2 ddd A1
UFDFPN-01
1. Drawing is not to scale. 2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be connected to any other voltage or signal line on the PCB, for example during the soldering process. 3. The circle in the top view of the package indicates the position of pin 1.
Table 15.
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 × 3 mm, package mechanical data
millimeters inches(1) Max 0.600 0.050 0.300 2.100 1.700 3.100 0.300 0.500 0.150 0.300 0.080 0.0118 0.0031 Typ 0.0217 0.0008 0.0098 0.0787 0.0630 0.1181 0.0079 0.0197 0.0177 Min 0.0177 0.0000 0.0079 0.0748 0.0591 0.1142 0.0039 0.0157 Max 0.0236 0.0020 0.0118 0.0827 0.0669 0.1220 0.0118 0.0197 0.0059
Symbol Typ A A1 b D D2 E E2 e L L1 L3 ddd(2) 0.550 0.020 0.250 2.000 1.600 3.000 0.200 0.500 0.450 Min 0.450 0.000 0.200 1.900 1.500 2.900 0.100 0.400
1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring.
28/33
M34E02
Package mechanical data Figure 15. TSSOP8 8-lead thin shrink small outline, package outline
D
8
5
c
E1 E
1
4
A1 A CP b e A2
L L1
TSSOP8AM
1. Drawing is not to scale. 2. The circle around the number 1 in the top view of the package indicates the position of pin 1. The numbers 4, 5 and 8 indicate the positions of pins 4, 5 and 8, respectively.
Table 16.
Symbol
TSSOP8 8-lead thin shrink small outline, package mechanical data
millimeters Typ. Min. Max. 1.200 0.050 1.000 0.800 0.190 0.090 0.150 1.050 0.300 0.200 0.100 3.000 0.650 6.400 4.400 0.600 1.000 0 8 8 2.900 6.200 4.300 0.450 3.100 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0 8 8 0.1142 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ. inches(1) Min. Max. 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 0.2598 0.1772 0.0295
A A1 A2 b c CP D e E E1 L L1 N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
29/33
Part numbering
M34E02
9
Part numbering
Table 17.
Example:
Ordering information scheme
M34E02 F DW 1 T P
Device type M34 = ASSP I2C serial access EEPROM
Device function E02 = 2 Kbit (256 × 8) SPD (serial presence detect) for DDR1 and DDR2
Operating voltage F = VCC = 1.7 to 3.6 V over 0C to 70 C(1) or F = VCC = 1.7 to 5.5 V over 40 C to 85 C(2)
Package MB = UDFDFPN8 (MLP8) DW = TSSOP8 (4.4 × 3 mm body size)
Temperature range 1 = 0 to 70 C 6 = 40 to 85 C
Option blank = Standard packing T = Tape & reel packing
Plating technology P or G = ECOPACK (RoHS compliant)
1. The 1.7 to 3.6 V operating voltage range is available only on temperature range 1 devices. 2. The 1.7 to 5.5 V operating voltage range is available only on temperature range 6 devices.
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.
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M34E02
Revision history
10
Revision history
Table 18.
Date 13-Nov-2003 01-Dec-2003
Document revision history
Revision 1.0 1.1 First release TSSOP8 4.4x3 package replaces TSSOP8 3x3 (MSOP8) package. Correction to sentence in "Setting the Write Protection". Correction to specification of tNS values. Always NoACK after Address and Data bytes in Table 6. Improvement in VIO and VCC (min) in Absolute Maximum Ratings table. IOL changed for test condition of VOL. MLP package mechanical data respecified. Soldering temperature information clarified for RoHS compliant devices. First public release Direct connection of E0, E1, E2 to VSS and VCC (see Chip Enable (E0, E1, E2) and Use within a DDR1/DDR2 DRAM module paragraphs). ZEiL and ZEiH parameters added to Table 11: Input parameters. E0, E1, E2 removed from the Parameter descriptions of VIL and VIH in Table 13: DC characteristics (for temperature range 6 devices). Document status promoted from Product Preview to full Datasheet. Datasheet title changed. Features revised. Plating Technology options updated in Table 17: Ordering information scheme. Resistance and capacitance renamed in Figure 4: Maximum RP value versus bus parasitic capacitance (C) for an I2C bus. Text in Power On Reset changed. Noise filter value in Table 11: Input parameters modified. ICC value 2mA, when Vcc=3/6V, added to Table 13: DC characteristics (for temperature range 6 devices). Changes
29-Mar-2004
1.2
14-Apr-2004
2.0
24-Nov-2004
3.0
11-Mar-2005
4.0
28 -Apr-2005
5.0
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Revision history Table 18.
Date
M34E02 Document revision history (continued)
Revision Changes In Table 14: AC characteristics: Frequency fC changed from 100kHz to 400kHz, related AC timings (tCHCL, tCLCH, tDXCX, tCLQV max, tCHDX, tDLCL, tCHDH, tDHDL) also modified. Power On Reset paragraph removed replaced by Internal device reset. Figure 3: Device select code inserted. ICC1 modified in Table 13: DC characteristics (for temperature range 6 devices). Note 3 added to Figure 14 and Note 2 added to Figure 15 All packages are ECOPACK (see text added under Description and Part numbering, TLEAD removed from Table 7: Absolute maximum ratings). Datasheet title and Features on page 1 modified: the device can be used with DDR1 and DDR2 DRAM configurations. Temperature range 6 added, operating voltage range VCC extended in device temperature range 6. IOL added to and TA modified in Table 7: Absolute maximum ratings. ILO, ICC and VIL modified in Table 13: DC characteristics (for temperature range 6 devices). Table 14: AC characteristics added. Table 13: DC characteristics (for temperature range 6 devices) modified. Figure 13: AC waveforms modified. Figure 4: Maximum RP value versus bus parasitic capacitance (C) for an I2C bus updated. Note removed below Figure 11: Serial presence detect block diagram. UFDFPN8 package specifications updated (see Table 15: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 × 3 mm, package mechanical data). Blank option removed under plating technology in Table 17: Ordering information scheme. Small text changes.
10-Apr-2006
6
18-Mar-2009
7
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M34E02
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